Technology
Minister for Electronics and Information Technology (MEITY), Ashwini Vaishnaw.
As part of its $10b incentive package, the Government of India is pursuing options to commercialise the ISRO-owned Semiconductor Lab (SCL) at Mohali.
Going by a report in Economic Times published one year ago, SCL was interested in upgrading its fabs from a 180nm technology node to a 65nm technology node and is said to have put in a proposal for the same when Ministry of Electronics and Information Technology (MEITY) opened an Expression of Interest last year.
However, what SCL currently has are tools that can process starting wafers of 200mm size. Experts say that for a 65nm technology node, both from the point of view of availability of equipment and that of operational efficiency, the fab will need to opt for a 300mm wafer production line.
To get a good return on investment as well as to be able to attain process yields of global standards, it will need to churn out a good number of processed wafers every month — a few tens of thousands, experts say.
It is unlikely that SCL will be able to transform itself to match global standards under the current setup.
A high-level delegation led by none other NSA Ajit Doval along with at least two Cabinet Ministers is said to have visited SCL in September this year.
Hardly any national medium carried the news; Punjab Kesari reported it and highlighted that the visit was somewhat secretive in nature and a report was submitted to the PMO, presumably with suggestions.
In the 15 December press release from GoI announcing the incentive scheme, the section about SCL read thus:
It appears from the language of the press release that the government may not be willing to put in much money for the proposed modernization and commercialization.
Note that currently, a few hundred crores of rupees are provided to SCL to keep it running and cater to chip orders, predominantly from government institutes or Indian academia.
However, a Joint Venture with an Indian business house or a reputed MNC fab (or both) may turn out to be a win-win situation. Being able to process 200mm wafers, albeit in low capacity, points to the fact that a small base is already established.
Taiwan-based Digitimes reports that shortage of chips made in fabs that run 200mm wafers (which typically means 90nm, 130nm, 180nm and so on technology nodes) may last up to 2025.
In addition, compound semiconductor and Silicon photonics specialty fabs also mostly process wafers of size 150mm or 200mm and this may be alternative or additional opportunities opening up for whichever fab partner SCL may eventually have a Joint Venture agreement with.
Much like the case of applications for the new fabs that will process 300mm wafers, the joint venture for SCL too has the possibility of fabs not getting into Joint Ventures directly but through an Indian business partner.
The fab partner(s) can help enhance the current technology and/or license new ones based on market and feasibility studies.
If some sources are to be believed, certain reputed Indian business groups are already in discussion with the government and executives from one or more of them may have already visited SCL as well.