TSMC Reaffirms Plans To Begin Volume Production Of 2 Nanometer Chip By 2025 As It Seeks To Maintain Decisive Edge Over Samsung, Intel

Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, reaffirmed that it will begin volume production of 2-nanometer(nm) chips by 2025 as the chip behemoth plans to beat competitors to be the first to deploy the advanced technology.

The chip manufacturing titan announced the timeline for 2nm production at its North America Technology Symposium in Santa Clara, California, which was held last week.

During the event, TSMC showcased its latest technology advances, including progress in 2nm technology and enhanced versions of 3-nm chip manufacturing process nodes, including N3P, N3X, and N3AE. 

The company also unveiled 3DFabric, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

The company said that the development of its 2nm technology, which is based on Gate-all-around (GAA) nanosheet transistor architecture, was making progress in yield and device performance and entering production in 2025 as scheduled.

The GAA nanosheet transistor architecture on which 2 nm tech is based is completely different from the Finfet infrastructure that is used for 3nm chips, currently the most advanced node in production and in more mature nodes.

GAA nanosheets are generally regarded as the next-generation transistor device that is set to be widely adopted by the semiconductor industry to continue logic scaling beyond the 5 nm technology node and beyond FinFETs

Unlike FinFETs, where higher current requires multiple side-by-side fins, the current-carrying capacity of GAA transistors is increased by stacking a few nanosheets vertically, with gate material wrapped around the channels. The nanosheet dimensions can be scaled so that transistors can be sized for the specific performance required.

The company's 2nm technology would be up to 15 per cent faster than its 3nm enhanced (N3E) process technology at the same power, with up to 30 per cent lower power use at the same speed and chip density of more than 15 per cent greater than N3E.

With 3nm technology now in volume production with the N3 process and the enhanced N3E version set to enter high-volume manufacturing in the second half of this year., TSMC said that it is adding new variants to the roadmap to suit customers' diverse needs.

Following N3E, TSMC would continue to optimize the N3 family's transistor density with 3nm performance-enhanced technology, which would build on N3E by offering better power, performance and density, the company said, adding that production would be ready in the second half of next year.

Its N3X product, which is tailored for high-performance computing applications and can support higher voltage and frequency — and therefore has stronger computing power — is to enter mass production in 2025, it said.

In addition, its Auto Early product would be available this year, offering automotive process design kits based on N3E, and allowing customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025, TSMC said.

As for its 2nm-process fabs, TSMC has said it will build a wafer plant in northern Taiwan's Hsinchu and later expand production to Taichung in central Taiwan.

The 2nm chip race

TSMC's reaffirming its 2nm roadmap comes amid its ongoing chip race with Samsung and Intel.

Samsung has said it will begin producing 2nm chips by 2025, while Intel is aiming to manufacture even more advanced chips by late 2024.

Intel has pledged to regain chip manufacturing tech leadership by 2025. The company first disclosed its 1.8nm technology -- what it calls 18A technology -- in mid-2021.

Japan, through a state-backed semiconductor venture Rapidus, also aims to get into 2nm chip technology manufacturing.