Taiwanese chipmaker TSMC has begun the mass production of next-generation 3nm semiconductor chip.

The company on Thursday (29 December) announced that 3nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 new construction site in the Southern Taiwan Science Park (STSP).

TSMC estimates that 3nm technology will create end products with a market value of $1.5 trillion within five years of volume production.

"Phases 1 through 8 of TSMC Fab 18 each have cleanroom area of 58,000 square meters, approximately double the size of a standard logic fab," the company said in a statement.

In addition to expanding 3nm capacity in Taiwan, TSMC is also building 3nm capacity at its Arizona site in the United States.

The company said that its 3nm process is the most advanced semiconductor technology in both power, performance, and area (PPA) and in transistor technology, and a full-node advance from the 5nm generation.

"Compared with the 5nm (N5) process, TSMC’s 3nm process offers up to 1.6X logic density gain and 30-35 per cent power reduction at the same speed, and supports the innovative TSMC FINFLEX architecture," the company said.

Earlier in June this year, Samsung had announced the start of the initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.

 Multi-Bridge-Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability, the company had said.

Samsung claims that the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO), which helps boost Power, Performance, Area (PPA) benefits.

Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45 per cent, improve performance by 23 per cent and reduce area by 16 per cent compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50 per cent, improve performance by 30 per cent and reduce area by 35 per cent, the company had said.