As Chips With 3nm Node Start Trickling In, Here Is A Quick Look At Transistor Shrinking Plan For The Next 15 Years
The quest for small transistors has so far reached the 5nm/4nm process nodes with Samsung expected to deliver a 3nm process node in the first half of 2022 and TSMC in the second half, and both are expected to deliver a 2nm node sometime in 2024-25.
While there are discussions on what a process node for semiconductor chip fabrication means in the modern context, as an executive summary, reducing the effective channel length between the source (of electrons) and the drain in a field effect transistor (FET) can ‘in theory’ achieve the following:
a) Increase speed — and hence the operating frequency,
b) Reduce power — ideally longer time for the same battery charge assuming same functions,
c) Increase density — as shrinking one feature leads to the possibility of shrinking other features and eventually making more transistors within the same area (or volume).
The quest for small transistors has so far reached the 5nm/4nm process nodes, currently done by Taiwan's TSMC and South Korea's Samsung. Samsung is expected to deliver a 3 nanometer (3nm) process node in the first half of 2022, TSMC in the second half, and both are expected to deliver a 2nm node sometime in 2024-25.
Intel has announced that it will not only "catch up" through its planned "Intel 4" in 2022 and "Intel 3" in 2023, but will even be ahead of both TSMC and Samsung by delivering 20A (20 Angstrom, equivalent of 2nm) in the first half of 2024, and 18A in the second half of 2024.
As dimensions shrink, to achieve the desired gate control and other parameters, the structure of the transistor changed from planar FET to FinFET at around 22nm (Intel) or 16/14nm (TSMC, Samsung, GlobalFoundries etc) and is again expected to change to gate all around (GAA) architecture — a prototype was first achieved in 2017 at 5nm by IBM-Samsung-GlobalFoundries. Samsung likely further developed and matured it and will offer as multi-bridge channel (MBC) FET at 3nm for high volume manufacturing.
Intel is calling its GAAFET as ribbonFET and is expected at its 2nm (20A) process node. TSMC is expected to stay with FINFET for its 3nm offering though as Anandtech points out "there could be a chance for TSMC to offer GAA-FETs on different versions of its 3nm nodes in the future if it wishes, however the company has not made any public statements at this time to this effect". So as of now only Samsung has announced GAAFET at 3nm and its yield percentages will be keenly watched.
As per a report in tomshardware, on 20 May 2022, Samsung "demonstrated the industry's first chip made using its 3 nm-class process technology featuring gate-all-around type transistors to Joe Biden and Yoon Suk-yeol, presidents of the US and South Korea".
The report goes on to say that "there is no word which 3nm chip was shown to the U.S. leader and whether it was a live demonstration or a static showcase. Keeping in mind that Samsung Foundry is about to start high volume manufacturing using its 3GAE node this quarter, it probably has working samples of its 3nm system-on-chip(s), though details of the demo are unknown".
Chinese technology medium gizchina recently reported that "Samsung is developing the next-generation flagship processor, Exynos 2300. The chip model number is S5E9935 and its codename is “Quadra”. According to a Sammobile report, the Samsung Exynos 2300 chip uses Samsung’s 3nm GAA manufacturing process".
It is likely that Samsung will use the newly-developed 3nm GAA process for its own SoC first before offering it for other customers through its foundry business. It will also be interesting to see how the competition shapes up once TSMC offers its 3nm which some feel may be "stretching the FINFET to its limits".
Meanwhile the roadmap for newer process nodes is ready beyond this decade. In its 2020 update, International Roadmap for Devices and Systems published possible device structures and specifications going up to 0.7 nm (7 Angstrom) in 2034.
In the 2022 version of its flagship event "Future Summit" on nanoelectronics advances and deep tech solutions on 17-18 May, leading semiconductor R&D organisation Interuniversity Microelectronics Centre (IMEC) of Belgium presented a transistor road map through 2036.
The roadmap that IMEC presented has a naming convention of "N" for the nanometer and "A" for Angstrom followed by the number and goes all the way to A2 (2 Angstrom) in 2036. Those interested in a more detailed analysis of this roadmap can read this article from tomshardware.
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